1. Field of the Invention
The present invention relates to error correcting decoding apparatuses, particularly, an error correcting decoding apparatus for decoding low-density parity-check codes.
2. Description of the Background Art
In creating a signal communication system, high speed communication, low power consumption, high communication quality (low bit error rate) and the like are required. The error correcting technique of detecting and correcting an error in reception codes is widely employed as one approach satisfying the aforementioned requirements in wireless, wired, and recording systems or the like.
In recent years, low-density parity-check (LDPC) codes and the sum-product decoding method are attracting attention as one approach in association with such error correcting technique. The decoding operation utilizing such LDPC codes is discussed in Non-Patent Document 1 of Chung et al. (S. Y. Chung et al., “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit” IEEE COMMUNICATIONS LETTERS, VOL. 5, No. 2, February 2001, pp. 58-60). This Non-Patent Document 1 teaches that decoding characteristics within 0.04 dB of the Shannon limit in the white Gaussian channel can be achieved utilizing irregular LDPC codes at the code rate of ½. Irregular LDPC codes refer to codes having a row weight (the number of 1 s in a row) and a column weight (the number of 1 s in a column) in a parity check matrix that are not constant. LDPC codes having a constant row weight and column weight in each row and each column are referred to as regular LDPC codes.
Although Non-Patent Document 1 shows mathematical algorithm of decoding LDPC codes according to the sum-product decoding method, there is no teaching of a specific circuit configuration to carry out the massive calculation.
Non-Patent Document 2 of Yeo et al. (E. Yeo et al., “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels” IEEE Trans. Magnetics, Vol. 37, No. 2, March 2001, pp. 748-755) provides a study on the circuit configuration of a decoding apparatus for LDPC codes. Non-Patent Document 2 teaches MAP (maximum a posteriori probability) algorithm defined on the trellis, i.e. BCJR algorithm, as the posteriori probability of the information symbol based on the reception series. The iteration in the forward direction and backward direction in the trellis is calculated for each state, and the posteriori probability is obtained based on the iteration values in the forward direction and backward direction. This calculation is carried out using add-compare-select-add units. A circuit is configured to generate a check matrix according to the sum-product decoding method for LDPC codes, and an estimate value is calculated using values from different check nodes.
Non-Patent Document 3 (Tadashi Wadayama, “Low-Density Parity-Check Codes and Decoding Method Thereof”, TECHNICAL REPORT OF IEICE, MR2001-83, December, 2001) illustrates LDPC codes and the sum-product decoding method, as well as the min-sum decoding method in the log domain. Non-Patent Document 3 shows that processing according to the f function of Gallager can be implemented by just the four basic operations of addition, minimize, positive/negative determination and positive/negative sign.
The aforementioned Non-Patent Document 2 and Non-Patent Document 3 disclose, in order to generate a parity check matrix to calculate a primary estimate word, a process including the steps of updating an external value log ratio α using the f function of Gallager according to the sum-product method, and then calculating the priori value log ratio β of the symbol based on the external value log ratio. Therefore, calculation of the Gallager function is time consuming and the circuit scale becomes larger.
The aforementioned Non-Patent Document 3 shows that the circuit configuration in implementation can be simplified in a short period of time by employing the min-sum decoding method that is a simplified version of the sum-product decoding method.
Moreover, specific methods of implementing the min-sum decoding method are disclosed in, for example, Patent Document 1 (Japanese Patent Laying-Open No. 2007-323515 and Patent Document 2 (Japanese Patent Laying-Open No. 2007-335992). These documents disclose a configuration in which a decoder performs parallel-processing on input data in units of code length to output decode data.
In order to apply the input data to a decoder that performs parallel-processing in such units of code length, a possible configuration is to convert the serial input data into parallel data of the code length, and then provide the data to the decoder through signal lines corresponding to the code length. However, the number of signal lines will become significant in such a configuration if the code length is long.
Another possible configuration is to apply input data of the code length serially into the decoder through one signal line. However, the time required for applying the data to the decoder will be increased in such a configuration.
A similar possible approach is to output decode data of the decode length serially in order to output decode data from the decoder to an external source. However, the time required for output from the decoder is time consuming in accordance with such a configuration.
There is also possible a configuration in which decode data of the decode length are output in parallel, and then output to an external source through signal lines of the decode length, followed by converting the parallel data of the decode length into serial data at an external source. However, this configuration is disadvantageous in that the number of signal lines required will be significant if the decode length is long.